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First published December 18, 2025 Application Aachen patent G – Physics

SOC PROGRAMMABLE LOGIC DEVICE

Espacenet Family 91481665

Abstract

A System-on-Chip Programmable Logic device, SoC PL (2), for performing a distributed and diverse inference task, the SoC PL (2) comprising a Host Processing System, PS (3), configured to receive an external request which relates to the inference task, and is accompanied by input data, and load configuration data of a deep neural network, DNN, corresponding to the received inference task upon receiving the external request; and a Programmable Logic, PL (7), including an input buffer (9) configured to store the loaded configuration data from the PS (3) under control of the PS (3), and a plurality of processing elements, PEs (11), configured to perform inference on the input data under use of the DNN when the PS (3) indicates that the input buffer (9) is ready, wherein the PEs (11) form a systolic array.

Inventors 2

  1. Haris Gacanin Aachen author as filed: Gacanin, Haris
  2. Mohsen Pourghasemian Aachen author as filed: Pourghasemian, Mohsen

Inventors are linked to an Aachen author when surname and first name match exactly one author.

Applicants

Cited papers 0 in the database

Non-patent literature as cited (7)
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Cited patents 0